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| Cover 88EM8010/88EM8011 Power Factor Correction Controller Datasheet Customer Use Only Doc. No. MV-S104861-01, Rev. - September 30, 2009 Marvell. Moving Forward Faster Document Classification: Proprietary 88EM8010/88EM8011 Datasheet For further information about Marvell(R) products, see the Marvell website: http://www.marvell.com Disclaimer No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, for any purpose, without the express written permission of Marvell. Marvell retains the right to make changes to this document at any time, without notice. Marvell makes no warranty of any kind, expressed or implied, with regard to any information contained in this document, including, but not limited to, the implied warranties of merchantability or fitness for any particular purpose. Further, Marvell does not warrant the accuracy or completeness of the information, text, graphics, or other items contained within this document. Marvell products are not designed for use in life-support equipment or applications that would cause a life-threatening situation if any such products failed. Do not use Marvell products in these types of equipment or applications. With respect to the products described herein, the user or recipient, in the absence of appropriate U.S. government authorization, agrees: 1) Not to re-export or release any such information consisting of technology, software or source code controlled for national security reasons by the U.S. Export Control Regulations ("EAR"), to a national of EAR Country Groups D:1 or E:2; 2) Not to export the direct product of such technology or such software, to EAR Country Groups D:1 or E:2, if such technology or software and direct products thereof are controlled for national security reasons by the EAR; and, 3) In the case of technology controlled for national security reasons under the EAR where the direct product of the technology is a complete plant or component of a plant, not to export to EAR Country Groups D:1 or E:2 the direct product of the plant or major component thereof, if such direct product is controlled for national security reasons by the EAR, or is subject to controls under the U.S. Munitions List ("USML"). At all times hereunder, the recipient of any such information agrees that they shall be deemed to have manually signed this document in connection with their receipt of any such information. Copyright (c) 1999-2009. Marvell International Ltd. All rights reserved. Marvell, Moving Forward Faster, the Marvell logo, Alaska, AnyVoltage, DSP Switcher, Fastwriter, Feroceon, Libertas, Link Street, PHYAdvantage, Prestera, TopDog, Virtual Cable Tester, Yukon, and ZJ are registered trademarks of Marvell or its affiliates. CarrierSpan, LinkCrypt, Powered by Marvell Green PFC, Qdeo, QuietVideo, Sheeva, TwinD, and VCT are trademarks of Marvell or its affiliates. Patent(s) Pending--Products identified in this document may be covered by one or more Marvell patents and/or patent applications. Doc. No. MV-S104861-01 Rev. - Page 2 Document Classification: Proprietary Copyright (c) 2009 Marvell September 30, 2009, 2.00 88EM8010/88EM8011 Power Factor Correction Controller Datasheet PRODUCT OVERVIEW The Marvell(R) 88EM8010/88EM8011 device is a high performance Power Factor Correction (PFC) Controller for boost applications. The device is used for universal PFC front-end boost converters in system or standalone products. Both devices work at fixed frequencies. 88EM8010 at 60kHz while 88EM8011 at 120kHz. Marvell advanced mixed signal technology ensures low Total Harmonic Distortion (THD). The IC operates under average Continuous Conduction Mode (CCM). The 88EM8010/88EM8011 PFC controller improves the steady state and transient performance through Marvell's innovative Digital Signal Processing (DSP) solution. The proprietary adaptive over-current protection has the ability to ensure almost constant power constraint and provides safety provisions including open loop and over voltage protection protocols. The internal voltage loop compensation and current loop control guarantees system stability and thus reduces the external component count and costs. The 8-pin SOIC package further facilitates the application design process, saving board space. The resultant simple system design and minimum cost makes 88EM8010/88EM8011 the ideal choice for PFC controllers. General Features Patented DSP control with adaptive loop coefficient Continuous Conduction Mode (CCM) operation Average current mode control Adaptive control loop achieves high power factor for a wide range of voltage and load conditions Adaptive over current protection for universal voltage Fixed frequency of operation High power factor and low harmonic distortion for a wide range of load conditions Up to 2A driver capability Minimal external components required Under voltage lockout (UVLO) Over voltage protection (OVP) Thermal shutdown Input line frequency range from 45Hz to 65Hz Applications Universal front-end PFC boost controller AC/DC adaptors and battery chargers Electronic Ballasts front-end with PFC Figure 1: PFC Boost Circuit Diagram L Bridge Retifier C IN PFC DR2 iL Rgate Q1 C O2 VO ut Load AC IN R cs Ra Rb SW R sen ISNS SGND R S1 Rc VDD CVDD VIN VDD 88EM8010/ 8011 PGND FB R S2 Copyright (c) 2009 Marvell September 30, 2009, 2.00 Document Classification: Proprietary Doc. No. MV-S104861-01 Rev. - Page 3 88EM8010/88EM8011 Datasheet THIS PAGE INTENTIONALLY LEFT BLANK Doc. No. MV-S104861-01 Rev. - Page 4 Document Classification: Proprietary Copyright (c) 2009 Marvell September 30, 2009, 2.00 Table of Contents Table of Contents Table of Contents ....................................................................................................................................... 5 List of Figures............................................................................................................................................. 7 List of Tables .............................................................................................................................................. 9 1 1.1 1.2 Signal Description ....................................................................................................................... 11 Pin Configurations ...........................................................................................................................................11 Pin Descriptions ..............................................................................................................................................11 2 2.1 2.2 2.3 Electrical Specifications ............................................................................................................. 13 Absolute Maximum Ratings ...........................................................................................................................13 Recommended Operating Conditions .............................................................................................................14 Electrical Characteristics ................................................................................................................................15 3 3.1 3.2 Functional Description................................................................................................................ 19 Overview .........................................................................................................................................................19 Signal Process and Functions.........................................................................................................................20 4 4.1 4.2 4.3 4.4 Functional Characteristics ......................................................................................................... 21 VDD Characteristics ........................................................................................................................................21 VFB Characteristics for Over Voltage Protection .............................................................................................23 Switching Frequency Characteristics ..............................................................................................................25 Over Current Threshold Characteristics..........................................................................................................26 5 5.1 5.2 5.3 Design and Applications Information ........................................................................................ 27 Input Voltage Resistor Divider on VIN Pin.......................................................................................................27 Voltage Loop & Output Voltage Feedback on FB Pin .....................................................................................30 Current Sensing and Over Current Protection ................................................................................................31 5.3.1 Current Sensing through ISNS Pin ...................................................................................................31 5.3.2 Over Current Limitation.....................................................................................................................33 SW Pin to MOSFET Gate ...............................................................................................................................33 VDD, Signal Ground (SGND) and Power Ground (PGND) .............................................................................34 Boost PFC Schematics ...................................................................................................................................35 5.4 5.5 5.6 6 6.1 Mechanical Drawings .................................................................................................................. 37 Mechanical Drawings ......................................................................................................................................37 7 7.1 7.2 Part Order Numbering/Package Marking .................................................................................. 39 Part Order Numbering ..................................................................................................................................39 Package Markings...........................................................................................................................................40 Copyright (c) 2009 Marvell September 30, 2009, 2.00 Document Classification: Proprietary Doc. No. MV-S104861-01 Rev. - Page 5 88EM8010/88EM8011 Datasheet G Revision History .......................................................................................................................... 41 Doc. No. MV-S104861-01 Rev. - Page 6 Document Classification: Proprietary Copyright (c) 2009 Marvell September 30, 2009, 2.00 List of Figures List of Figures Figure 1: PFC Boost Circuit Diagram ................................................................................................................3 1 Signal Description ........................................................................................................................... 11 Figure 2: SOIC-8 Pin Diagram (Top View).......................................................................................................11 2 3 Electrical Specifications ................................................................................................................. 13 Functional Description.................................................................................................................... 19 Figure 3: Top Level Block Diagram..................................................................................................................19 4 Functional Characteristics.............................................................................................................. 21 Figure 4: Figure 5a: Figure 5b: Figure 6a: Figure 6b: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: Figure 16: Figure 17: Figure 18: IDD Quiescent (IDD_QST) vs. VDD ...................................................................................................21 IDD vs. VDD (VDD_ON) ........................................................................................................................21 IDD vs. VDD (VDD_ON), VFB Enable...................................................................................................21 IDD Sleep (IDD_OP) vs. Temperature...............................................................................................22 IDD Operation (IDD_OP) vs. Temperature ........................................................................................22 VDD On/Off vs. Temperature ...........................................................................................................22 IDD vs. VFB (OVP) .............................................................................................................................23 VFB_OVP vs. Temperature ..............................................................................................................23 VFB_OVP Hysteresis vs. Temperature ............................................................................................23 VFB_OVP_LATCH vs. Temperature ................................................................................................23 Normal Regulation Reference (VFB_REG) vs. Temperature ...........................................................24 IDD vs. VFB (Enable) .......................................................................................................................24 VFB_EN (Enable) vs. Temperature ..................................................................................................24 VFB_EN Hysteresis vs. Temperature ...............................................................................................24 Switching Frequency vs. Temperature .............................................................................................25 Over Current (VIOVER) vs. Input Voltage VIN Peak Value).............................................................26 Over Current (VIOVER) vs. Temperature .........................................................................................26 5 Design and Applications Information ............................................................................................ 27 Figure 19: Figure 20: Figure 21: Figure 22: Figure 23: Figure 24: Figure 25: Figure 26: Figure 27: Internal Block for Zero-cross Detection, Brown-out Protection .........................................................28 Peak Detecting Signal for Predictive Sinusoidal AC Voltage............................................................29 Input Voltage Resistor Divider Layout Guidelines ............................................................................30 Output Voltage Resistor Divider .......................................................................................................31 Current Sensing Circuit.....................................................................................................................31 SW Pin Layout Guidelines ................................................................................................................33 VDD Decoupling Capacitor and Ground Layout Guidelines .............................................................34 64W/450V Front-End Boost PFC Schematic ....................................................................................35 300W/380V Front-End Boost PFC Schematic ..................................................................................36 6 Mechanical Drawings ...................................................................................................................... 37 Figure 28: 8-Pin SOIC Mechanical Drawing ......................................................................................................37 Copyright (c) 2009 Marvell September 30, 2009, 2.00 Document Classification: Proprietary Doc. No. MV-S104861-01 Rev. - Page 7 88EM8010/88EM8011 Datasheet 7 Part Order Numbering/Package Marking....................................................................................... 39 Figure 29: Figure 30: 88EM8010/88EM8011 Sample Ordering Part Number ....................................................................39 Package Marking and Pin 1 Location ...............................................................................................40 G Revision History ............................................................................................................................... 41 Doc. No. MV-S104861-01 Rev. - Page 8 Document Classification: Proprietary Copyright (c) 2009 Marvell September 30, 2009, 2.00 List of Tables List of Tables 1 Signal Description ............................................................................................................................ 11 Table 1: Table 2: Pin Descriptions ................................................................................................................................11 Pin Descriptions ................................................................................................................................12 2 Electrical Specifications .................................................................................................................. 13 Table 3: Table 4: Table 5: Absolute Maximum Ratings ..............................................................................................................13 Recommended Operating Conditions...............................................................................................14 Electrical Characteristics ..................................................................................................................15 3 4 5 Functional Description..................................................................................................................... 19 Functional Characteristics............................................................................................................... 21 Design and Applications Information ............................................................................................. 27 Table 6: Table 7: Current Sensing Resistor Selection ..................................................................................................32 Current Sensing Resistor Selection Reference ................................................................................32 6 7 G Mechanical Drawings ....................................................................................................................... 37 Part Order Numbering/Package Marking........................................................................................ 39 Table 8: 88EM8010/88EM8011 Part Order Options .......................................................................................39 Revision History ............................................................................................................................... 41 Table 9: Revision History ................................................................................................................................41 Copyright (c) 2009 Marvell September 30, 2009, 2.00 Document Classification: Proprietary Doc. No. MV-S104861-01 Rev. - Page 9 88EM8010/88EM8011 Datasheet THIS PAGE INTENTIONALLY LEFT BLANK Doc. No. MV-S104861-01 Rev. - Page 10 Document Classification: Proprietary Copyright (c) 2009 Marvell September 30, 2009, 2.00 Signal Description Pin Configurations 1 1.1 Signal Description Pin Configurations Figure 2: SOIC-8 Pin Diagram (Top View) PGND 1 8 SW SGND 2 7 VDD ISNS 3 6 NC VIN 4 5 FB/EN 1.2 Pin Descriptions Table 1: Pi n # 1 2 3 4 5 6 7 8 Pin Descriptions P in N a m e PGND SGND ISNS VIN FB/EN NC VDD SW P in Ty p e Ground Ground Input Input Input NC Supply Output Pin Description Power Ground Signal Ground Current Sense Voltage Input Feedback/Enable/Shutdown No Connect IC Supply Voltage Switch Copyright (c) 2009 Marvell September 30, 2009, 2.00 Document Classification: Proprietary Doc. No. MV-S104861-01 Rev. - Page 11 88EM8010/88EM8011 Datasheet Table 2: Pi n # 1 Pin Descriptions P in N a m e PGND D e sc r ip ti o n Power Ground Connected to the source of the primary MOSFET. The PCB trace from the power ground to the source of the MOSFET must be kept as short as possible. To avoid any switching noise interruption on signal processing, PGND and SGND remain separate inside the IC. Signal Ground Must be connected to the power ground with Kelvin sensing connection, so that SGND has dedicated trace and connections and provides noiseless environment for the signal processing. Current Sense Sense resistor varies for different loads. Pin used for current shaping and for over current protection. Please refer to Section 5, Design and Applications Information, on page 27. Voltage Input * Connects to resistive divider at input AC line "phase" to GND. Voltage applied is a half rectified sine wave scaled down by the input resistive divider. * Voltage input pin is a high impedance input pin. An impedance of 2M (typical) is recommended to be designed from the input AC "phase" to GND in order to reduce the standby power. Higher impedance is preferred with the right PCB design on this pin signal. * Voltage is compared with a threshold reference (VVIN_BR) to detect the zero-cross location of the input sine wave and synthesize (regenerate) the input sine wave. This sine wave is used to generate the current reference. * Brown-out protection1 function is also provided by this pin. A resistor devider with a 100:1 ratio from the highside resistor to the lowside resistor is corresponding to the "brown-out protection" input voltage as 50V (RMS). Increasing that raio will increase the "brown-out voltage". Please refer to footnote1 for further explaination. Feedback The output voltage is scaled to 2.5V with 100% rated value. Transition from soft start to normal regulation at 87.5% rated VFB. Over voltage shutdown SW gate signal at 107% rated VFB and recover once below VFB_OVP. There is another threshold (VFB_OVP_LATCH) as 3.77V on the FB pin. When FB Voltage reaches VFB_OVP_LATCH, SW signal is shutdown and latched until another VDD power on reset. EN: Enable/Shutdown * At VFB>VFB_EN (Table 5) IC is enabled. * Pulling this pin to VFB < VFB_SHDN (Table 5) disables the chip back to sleep mode Note: A 200k resistor inside IL between FB pin to SGND. This should be included in the calculation for the design of the output voltage feedback resistor devider. No Connect Float this pin. IC Supply Voltage Nominal voltage is 12V (typical) and the Under Voltage Lockout (UVLO) for VDD SGND 3 ISNS 4 VIN 5 FB/EN 6 7 NC VDD 8 SW 1. Brown-out voltage is determined by Ra , Rb, and Rc as shown in Figure 1. Please refer to Section 5.1 for a further understanding. Doc. No. MV-S104861-01 Rev. - Page 12 Document Classification: Proprietary Copyright (c) 2009 Marvell September 30, 2009, 2.00 Electrical Specifications Absolute Maximum Ratings 2 2.1 Table 3: Electrical Specifications Absolute Maximum Ratings Absolute Maximum Ratings1 NOTE: Stresses above those listed in Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. Sy m b o l VDD VIsns VVIN VFB VSW P a r a m e t er Power Supply (Voltage to PGND=SGND) Voltage at ISNS pin Voltage at VIN pin Voltage at FB pin Output Driver Voltage Thermal Resistance SOIC-8 Thermal Resistance DIP-8 TA TJ TSTOR VESD Operating Ambient Temperature Range2 Maximum Junction Temperature Storage Temperature Range ESD Rating3 -65 -40 Min -0.3 -0.5 -0.3 -0.3 Max 18 3 5.5 5.5 18 156.5 89.5 85 125 150 2 U n i ts V V V V V C/W C/W C C C kV JA 1. Exceeding the absolute maximum rating may damage the device. 2. Specifications over the -40C to 85C operating temperature ranges are assured by design, characterization and correlation with statistical process controls. 3. Devices are ESD sensitive. Handling precautions recommended. Human Body model, 1.5k in series with 100pF. Copyright (c) 2009 Marvell September 30, 2009, 2.00 Document Classification: Proprietary Doc. No. MV-S104861-01 Rev. - Page 13 88EM8010/88EM8011 Datasheet 2.2 Table 4: Sy m b o l TA TJ Recommended Operating Conditions Recommended Operating Conditions1 P a r a m e te r Operating Ambient Temperature2 Junction Temperature M in -40 -20 Ty p Max 85 125 U ni ts C C 1. This device is not guaranteed to function outside the specified operating temperature range. 2. Over the -40C to 85C operating temperature ranges are assured by design, characterization, and correlation with statistical process controls. Doc. No. MV-S104861-01 Rev. - Page 14 Document Classification: Proprietary Copyright (c) 2009 Marvell September 30, 2009, 2.00 Electrical Specifications Electrical Characteristics 2.3 Table 5: Sy m b o l VDD Supply VDD VDD_ON VDD_UVLO VDD_UVLO_HYS IDD_QST IDD_OP Electrical Characteristics Electrical Characteristics Parameter C on d it io n s M in Ty p Max Units NOTE: A 12V supply voltage is applied and the ambient temperature (TA) = 25C. Supply Voltage VDD Power On Threshold VDD Power Off Threshold (UVLO) VDD_UVLO Hysteresis VDD Quiescent Current1 VDD Operating Current VDD = 12V VDD = 12V; CGate = 1nF FSW = 118kHz VIN= 0 First time power on operation After VDD is powered up and running 7.0 12 11.9 7.0 16 12.22 7.2 5.3 95 V V V V A mA 4.7 5.2 6.2 Thermal Shutdown TSD TSD_HYS Gate Driver VG_HI Minimum Gate High Voltage2 VDD = 12V CGate = 1nF Sourcing 500mA VDD = 12V CGate = 1nF Sinking 500mA Sourcing 75mA T=25 C Sinking 20mA T=25 C CGate = 10 nF VDD = 12 V CGate = 1 nF CGate = 10 nF tF Fall Time CGate = 1 nF CGate = 10 nF 2.0 35 125 35 145 2.4 2.0 10.0 V Thermal Shutdown Hysteresis for Thermal Shutdown 150 25 C C VG_LO Maximum Gate Low Voltage3 2.0 V RDSON Gate Drive Resistance Gate Drive Resistance A ns ns ns ns ISW_PK tR Driver Peak Current Rise Time Copyright (c) 2009 Marvell September 30, 2009, 2.00 Document Classification: Proprietary Doc. No. MV-S104861-01 Rev. - Page 15 88EM8010/88EM8011 Datasheet Table 5: Sy m b o l DMAX Electrical Characteristics Parameter Maximum Duty Cycle C on d it io n s M in Ty p Max 97 Units % NOTE: A 12V supply voltage is applied and the ambient temperature (TA) = 25C. Feedback/Overvoltage VFB_REG VFB_EN Normal Regulation Reference VFB at Enable Threshold IC powered on IC powered on by VDD_ON. Transition from sleep mode to IC enable at Enable Threshold of VFB_EN IC powered on by VDD_ON. Transfe from IC enable to sleep mode at Shutdown Threshold of VFB_SHDN 2.55 0.278 V V VFB_SHDN VFB at Shutdown Threshold 0.248 V VFB_EN_HYS VFB_OVP VFB_OVP_HYS VFB_OVP_LATCH VFB at Enable Hysteresis Over Voltage Protection Threshold Over Voltage Protection Hysteresis Over Voltage Protection Latch At 107% of VFB_REG. 2.67 0.102 0.03 2.71 2.75 0.108 3.77 V V V V Current Sensing and Current Protection4 VIOVER_TH1 Over Current Threshold Zone 15 Over Current Threshold Zone 25 Over Current Threshold Zone 35 Over Current Threshold Zone 45 Peak value of half-sine voltage at VIN: 1.26 329 mV VIOVER_TH3 269 mV VIOVER_TH4 202 mV 88EM8010 Switching Frequency Oscillator FSW Frequency 59 kHz 88EM8011 Switching Frequency Oscillator FSW Frequency 100.3 118 135.7 kHz 1. Quiescent Current: VDD power supply current before VDD first time reaches VDD_On. Doc. No. MV-S104861-01 Rev. - Page 16 Document Classification: Proprietary Copyright (c) 2009 Marvell September 30, 2009, 2.00 Electrical Specifications Electrical Characteristics 2. Considering the voltage drop on the internal driver MOSFET during current sourcing. 3. Considering the voltage drop on the internal driver MOSFET during current sinking. 4. To achieve almost constant power limit for the universal input range, current protection self-adjusts thresholds in four zones of input voltage levels. A margin of 50% compared to the rated current is considered for the threshold current values. 5. Threshold of negative voltage drop across Rsns due to instantaneous current 6. With input divider ratio of 1/100, these values are equivalent to 90 Vrms Doc. No. MV-S104861-01 Rev. - Page 17 88EM8010/88EM8011 Datasheet THIS PAGE INTENTIONALLY LEFT BLANK Doc. No. MV-S104861-01 Rev. - Page 18 Document Classification: Proprietary Copyright (c) 2009 Marvell September 30, 2009, 2.00 Functional Description Overview 3 3.1 Functional Description Overview The 88EM8010/88EM8011 is a high performance, low-cost with minimum component count Power Factor Correction (PFC) Controller. The device is used for Universal PFC front-end boost converters in systems or standalone products. The high performance of 88EM8010/88EM8011 is accompanied with its small system size and simplicity of application. Figure 3 shows the top level block diagram. Figure 3: Top Level Block Diagram 88EM8010/8011 Oscillator Clock Over Temperature T_over Vo_over I_over Protection Management Fault Driver Disable Current Protection ISNS FB Current Amplifier MUX Switcher & ADC DSP Core Vo_over Output Voltage Level Detect State Machine Gate Driver SW VIN Zero Cross Detect Current Protection Threshold Selection Power Distribution and Bandgaps Serial Data Interface Startup Setting or Frequency Setting PGND SGND VDD Copyright (c) 2009 Marvell September 30, 2009, 2.00 Document Classification: Proprietary Doc. No. MV-S104861-01 Rev. - Page 19 88EM8010/88EM8011 Datasheet 3.2 Signal Process and Functions The 88EM8010/88EM8011 boost power board includes three inputs: Resistive divider signal from AC line voltage Feedback from the output DC bus Voltage across the current sense resistor The input phase voltage to ground (half rectified sine wave) scaled down by the input resistive divider is applied to pin VIN. This signal used for estimation of the AC line voltage and regeneration of the AC sine wave. It is also used for voltage level detection that produces adaptive multiple thresholds for the over current limit and guarantees a constant power limit from the AC source. Signal from the DC bus voltage through the output resistor devider and Analog-to-Digital Converter (ADC) provides the feedback data for the voltage PI control loop. HF switching current pulse signal is retrieved from the voltage drop across the current sense resistor. Current sensing signal is negative to the ground. This signal after HF noise filter and fixed gain amplification, is transferred through the ADC to the digital current loop and the current error amplifier. The reference current for the current control PI loop is provided by multiplying the voltage error amplifier output and the regenerated sinusoidal line voltage information. Doc. No. MV-S104861-01 Rev. - Page 20 Document Classification: Proprietary Copyright (c) 2009 Marvell September 30, 2009, 2.00 Functional Characteristics VDD Characteristics 4 4.1 Functional Characteristics The following applies unless otherwise noted: VIN = 60Hz half-wave sinusoidal from 0V to the peak voltage (VPK) given in the test conditions of each graph. TA = 25C. All measurement readings are typical. VDD Characteristics Figure 4: IDD Quiescent (IDD_QST) vs. VDD 100 90 80 70 60 50 40 30 20 10 0 0 2 4 6 VDD (V) 8 10 12 IDD (A) Test Conditions: VIN = 0V FSW = 118kHz VFB = 0V CGate = 1nF V_Isns = 0V Figure 5a: IDD vs. VDD (VDD_ON) 0.18 0.16 0.14 0.12 IDD (mA) 0.10 0.08 0.06 0.04 0.02 0.00 0 5 10 VDD (V) 15 20 VDD Falling VDD Rising Figure 5b: IDD vs. VDD (VDD_ON), VFB Enable 7 6 5 IDD (mA) 4 3 2 1 0 0 2 4 6 8 VDD (V) 10 12 14 16 VDD Falling VDD Rising Test Conditions: VIN = 0V FSW = 118kHz VFB = 0V CGate = 1nF V_Isns = 0V Test Conditions: VIN = 0V FSW = 118kHz VFB = 2.4V CGate = 1nF V_Isns = 0V Copyright (c) 2009 Marvell September 30, 2009, 2.00 Document Classification: Proprietary Doc. No. MV-S104861-01 Rev. - Page 21 88EM8010/88EM8011 Datasheet Figure 6a: IDD Sleep (IDD_OP) vs. Temperature 0.25 Figure 6b: IDD Operation (IDD_OP) vs. Temperature 7 0.20 6 IDD (mA) 0.15 5 IDD (mA) -40 -20 0 20 Temperature ( C) 40 60 80 0.10 0.05 0.00 4 3 2 1 0 -40 -20 0 20 Temperature ( C) 40 60 80 Test Conditions: VDD = 12V VIN = 0V FSW = 118kHz VFB = 0V CGate = 1nF V_Isns = 0V Test Conditions: VDD = 12V VIN = 0V FSW = 118kHz VFB = 2.4V CGate = 1nF V_Isns = 0V Figure 7: VDD On/Off vs. Temperature 14 12 10 VDD (V) 8 6 4 2 0 -40 -20 0 20 Temperature ( C) 40 On Off Hysteresis 60 80 Test Conditions: VIN = 0V FSW = 118kHz FFB = 2.4V CGate = 1nF V_Isns = 0V Doc. No. MV-S104861-01 Rev. - Page 22 Document Classification: Proprietary Copyright (c) 2009 Marvell September 30, 2009, 2.00 Functional Characteristics VFB Characteristics for Over Voltage Protection 4.2 VFB Characteristics for Over Voltage Protection Figure 9: VFB_OVP vs. Temperature 3.0 2.5 2.0 V F B (V ) 1.5 1.0 0.5 0.0 -40 -20 0 20 Temperature ( C) 40 60 80 Figure 8: IDD vs. VFB (OVP) 6.5 6.0 5.5 IDD (mA) 5.0 4.5 4.0 3.5 3.0 2.0 2.2 2.4 VFB (V) 2.6 2.8 3.0 VFB Falling VFB Rising OVP Threshold Recovery Threshold Test Conditions: VDD = 12V VIN = 0V FSW = 118kHz CGate = 1nF V_Isns = 0V Test Conditions: VDD = 12V VIN = 0V FSW = 118kHz CGate = 1nF V_Isns = 0V Figure 10: VFB_OVP Hysteresis vs. Temperature 0.30 0.25 Figure 11: VFB_OVP_LATCH vs. Temperature 4.0 3.5 3.0 0.20 VFB (V) VFB (V) 2.5 2.0 1.5 1.0 0.15 0.10 0.05 0.00 -40 -20 0 20 Temperature ( C) 0.5 0.0 40 60 80 -40 -20 0 20 Temperature (C) 40 60 80 Test Conditions: VDD = 12V VIN = 0V FSW = 118kHz CGate = 1nF V_Isns = 0V Test Conditions: VDD = 12V VIN = 0V FSW = 118kHz CGate = 1nF V_Isns = 0V Copyright (c) 2009 Marvell September 30, 2009, 2.00 Document Classification: Proprietary Doc. No. MV-S104861-01 Rev. - Page 23 88EM8010/88EM8011 Datasheet Figure 12: Normal Regulation Reference (VFB_REG) vs. Temperature 3.0 2.9 2.8 Figure 13: IDD vs. VFB (Enable) 7 6 5 IDD (mA) 4 3 2 1 0 0.0 0.2 0.4 VFB (V) 0.6 0.8 1.0 VFB Falling VFB Rising 2.7 VFB (V) 2.6 2.5 2.4 2.3 2.2 2.1 2.0 -40 -20 0 20 Temperature (C) 40 60 80 Test Conditions: VDD = 12V VIN = 2V FSW = 118kHz CGate = 1nF V_Isns = 0V Test Conditions: VDD = 12V VIN = 0V FSW = 118kHz CGate = 1nF V_Isns = 0V Figure 14: VFB_EN (Enable) vs. Temperature 0.40 0.35 0.30 VFB (V ) 0.25 0.20 0.15 0.10 0.05 0.00 -40 -20 0 20 Temperature ( C) 40 60 80 Figure 15: VFB_EN Hysteresis vs. Temperature 0.30 Enable High VFB_En_hys (V) 0.25 0.20 Enable Low 0.15 0.10 0.05 0.00 -40 -20 0 20 Temperature ( C) 40 60 80 Test Conditions: VDD = 12V VIN = 0V FSW = 118kHz CGate = 1nF V_Isns = 0V Test Conditions: VDD = 12V VIN = 0V FSW = 118kHz CGate = 1nF V_Isns = 0V Doc. No. MV-S104861-01 Rev. - Page 24 Document Classification: Proprietary Copyright (c) 2009 Marvell September 30, 2009, 2.00 Functional Characteristics Switching Frequency Characteristics 4.3 Switching Frequency Characteristics Figure 16: Switching Frequency vs. Temperature 140 120 Frequency (kHz) FSW (8011) 100 80 60 40 20 0 -40 -20 0 20 40 60 80 Temperature (C) FSW (8010) Test Conditions: VDD = 12V VIN = 0V VFB = 2.4V CGate = 1nF V_Isns = 0V Copyright (c) 2009 Marvell September 30, 2009, 2.00 Document Classification: Proprietary Doc. No. MV-S104861-01 Rev. - Page 25 88EM8010/88EM8011 Datasheet 4.4 Over Current Threshold Characteristics Figure 17: Over Current (VIOVER) vs. Input Voltage VIN Peak Value) 0.50 0.45 0.40 0.35 V C S (V ) 0.30 0.25 0.20 0.15 0.10 0.05 0.00 0 1 2 VIN (V) 3 4 5 Test Conditions: VDD = 12V FSW = 118kHz VFB = 2.4V CGate = 1nF V_Isns = 0V Figure 18: Over Current (VIOVER) vs. Temperature 450 400 350 300 VCS (V) VIN = 1.5V VIN = 2.25V VIN = 3V VIN = 3.7V 250 200 150 100 50 0 -40 -20 0 20 Temperature ( C) 40 60 80 Test Conditions: VDD = 12V FSW = 118kHz VFB = 2.4V CGate = 1nF V_Isns = 0V Doc. No. MV-S104861-01 Rev. - Page 26 Document Classification: Proprietary Copyright (c) 2009 Marvell September 30, 2009, 2.00 Design and Applications Information Input Voltage Resistor Divider on VIN Pin 5 Design and Applications Information The boost converter is the most popular topology for two stage front-end PFC pre-regulator system. The 88EM8010/88EM8011 chip control algorithm uses Average Current Mode Control for power factor correction applications based on Boost topology with low harmonic distortion and good noise immunity. The IC senses the output voltage and forces it to follow the reference voltage to produce a stable DC output voltage matching the design requirement. It also senses the inductor current and forces the average signal of the inductor current to follow the sinusoidal current reference, therefore achieving unity power factor. Marvell's innovative PFC control technology improves the performance of the Boost converter used in PFC applications. The 88EM8010/88EM8011 provides the higher drive current capability than that of the competitors' ICs. The 88EM8010/8011 also achieves high power factor/low THD at high line low load condition which is benefited from Marvell mixed signal technology. The Boost PFC solution based on the 88EM8010/88EM8011 provides customers with the simplest structure, lowest cost and best performance compared with the other industry solutions currently on the market. The following sections provide guidelines for the application design, component selection, and board layout in order to improve front-end Boost PFC performance. There are three analog input signals listed below are required from the power train to the controller IC 88EM8010/88EM8011. 1. 2. 3. Input voltage signal at VIN pin is a half sinusoidal waveform. It is fed into the VIN pin through the input voltage resistor divider. This is for the line frequency zero-cross detection for PFC. Output voltage signal at FB pin is the output voltage through the resistor divider to feedback on FB pin. This is for the voltage loop regulation. Current sensing signal through the sensing resistor to the ISNS pin. This is for the average current mode control to achieve a good sinusoidal current waveform and high power factor. The output signal from the 88EM8010/88EM8011 is the PWM gate drive signal from the SW pin. The switching frequency on the 88EM8010 device is fixed to 60kHz (typical) while the 88EM8011 is fixed to 120kHz (typical). Both device tolerances are shown in Table 5, Electrical Characteristics, on page 15. 5.1 Input Voltage Resistor Divider on VIN Pin An accurate peak detection signal and zero-cross detection for regenerating the input sinusoidal voltage is the most important issue for a proper current shaping and total harmonic distortion (THD) improvement. If the threshold reference is too high, near the peak area, the calculation may lose accuracy because of the low slope. On the other hand, if the threshold reference is too low due to the possible distortions near the zero-crossing, there could be an error on zero-cross detection. For a universal input voltage range (85VAC~270VAC) the optimum accuracy would be achieved if the threshold level is around 30 degree of the line cycle. Copyright (c) 2009 Marvell September 30, 2009, 2.00 Document Classification: Proprietary Doc. No. MV-S104861-01 Rev. - Page 27 88EM8010/88EM8011 Datasheet Figure 19: Internal Block for Zero-cross Detection, Brown-out Protection 88EM8010 /8011 Brown-Out Protection AC IN Predictive Sinusoidal AC Voltage Vline _ pk Phase ( ) Ra Rb Rc VIN Peak detecting pulse Zero Crossing Power Limit Threshold Selection To get a proper sinusoidal AC voltage, UVLO, and peak voltage detection, we need to choose the right value for the sensing resistors: Ra, Rb, and Rc (See Figure 19). If the value is too small there will be higher power loss and if the value is too big the resistor will not properly work due to the picking noise of the VIN signal. The recommended values are shown below: R a + R b 100 1.8M = = Rc 1 18k Equation (1) For the input voltage resistor divider, the appropriate combination based on the voltage / power rating of the resistors should also be considered. Doc. No. MV-S104861-01 Rev. - Page 28 Document Classification: Proprietary Copyright (c) 2009 Marvell September 30, 2009, 2.00 Design and Applications Information Input Voltage Resistor Divider on VIN Pin Figure 20: Peak Detecting Signal for Predictive Sinusoidal AC Voltage Vline_pk VVIN_BR = 0.72V (Typ.) V ( ) = Vline_pk x sin Half line cycle Half line cycle Vline_pk N M Peak detecting Pulse N As can be seen in Figure 20, the internal peak detecting circuit generates peak detecting pulse through the inside comparator which has a threshold voltage of 0.72V (typical). Processing of this pulse in DSP core calculates the mid-point (peak point) and the zero-crossing point of the sinusoidal waveform. The phase angle of is calculated using the width of the high and low signal M&N. N = ( - 2 ) M = ( + 2 ) (M - N) = ------------------4 Peak value of the sinusoidal waveform is introduced by the relation: Equation (2) Equation (3) Equation (4) V() V line_pk = --------------sin ( ) Equation (5) The signal that appears on the VIN pin is a half sinusoidal voltage waveform and its peak line value has to be higher than VVIN_BR of 0.72V (typical) for normal operation. Whenever the VVIN_BR is less than 0.72V at the peak line value, it is considered as a Brown-out condition. The IC only generates 6% duty during the brown-out condition. To adjust the brown-out protection point, the resistance value of Ra, Rb and Rc can be changed. With the recommended resistor values in Equation (1) the brown-out protection voltage is 72V peak value, which is around a 50V RMS value for the input line voltage. The layout of Rb, Rc and Cc should be kept as close as possible to the VIN pin, as shown in Figure 21 in order to have a proper layout on the input voltage resistor divider and to avoid noise picking. It is also recommended that a 0.1nF-10nF capacitor is connected between the VIN pin and ground with the layout also close to this pin. Copyright (c) 2009 Marvell September 30, 2009, 2.00 Document Classification: Proprietary Doc. No. MV-S104861-01 Rev. - Page 29 88EM8010/88EM8011 Datasheet Figure 21: Input Voltage Resistor Divider Layout Guidelines Ra ISNS Rb Rc Cc V IN VDD Keep layout of Rb, Rc and Cc as close as possible to Vin pin to have high noise immunity SW 88EM8010/ 8011 FB PGND SGND 5.2 Voltage Loop & Output Voltage Feedback on FB Pin The 88EM8010/88EM8011 IC integrates the voltage loop into digital DSP core. This internal voltage loop has the lower corner frequency for the PFC requirement. The FB pin is the internal voltage loop feedback signal input. The voltage reference of the IC is 2.5V for the rated output voltage. It is well known that the front-end PFC with Boost topology has to maintain low enough bandwidth (less than 20Hz) in order to achieve a good sinusoidal current waveform and power factor under a wide input voltage and load condition. In order to achieve a good sinusoidal current waveform and power factor, the voltage loop regulation coefficient should also be designed properly corresponding to the different input voltages. The adaptive voltage loop coefficient is designed inside the IC to select different voltage regulation parameters corresponding to the different input voltage. This achieves a much better power factor and sinusoidal current waveform compared to any of PFC power system on the market now. The design of RS1and RS2, as shown in Figure 22, is based on the rated output voltage and the power loss of the resistor divider. In order to keep low power consumption on the resistor divider and good signal to noise immunity, a total resistance of several M is recommended for the pair of resistors RS1 and RS2. Because there is a 200k resistor inside of the IC between the FB pin to the SGND, the value of RS1 and RS2 is designed based on Equation (6) as: V out - V ref V ref V ref -------- + -------- = -----------------------R s2 R 0 R s1 Where Vref is 2.5V and R0 is 200k. Equation (6) Doc. No. MV-S104861-01 Rev. - Page 30 Document Classification: Proprietary Copyright (c) 2009 Marvell September 30, 2009, 2.00 Design and Applications Information Current Sensing and Over Current Protection Figure 22: Output Voltage Resistor Divider VOUT RS1 88EM8010/ 8011 FB R S2 5.3 5.3.1 Current Sensing and Over Current Protection Current Sensing through ISNS Pin The voltage drop on the current sense resistor should be kept very small in order to reduce the power consumption on the sense resistor (Rsen). The voltage drop (Vsen) across resistor (Rsen) represents the Boost current signal. As shown in Figure 23. Vsen is feedback to the ISNS pin through a resistor RCS, which is around 200. This resistor is necessary for the protection of the ISNS pin during inrush and lightning surge condition. The resistor (Rsen) should be designed and calculated such as the example in Table 6 where Rsen is designed for a 64W Boost converter. The specification are: output power = 64W, input voltage range = 85-264V, output voltage = 450V, 30% margin of over current on top of the normal current. Figure 23: Current Sensing Circuit L DR2 iL Q1 C O2 Load Vsen R cs R sen Using Kelvin sensing connection for current sensing signal and SGND with separate trace from PGND ISNS SGND SW VIN VDD 88EM8010/ 8011 PGND FB Copyright (c) 2009 Marvell September 30, 2009, 2.00 Document Classification: Proprietary Doc. No. MV-S104861-01 Rev. - Page 31 88EM8010/88EM8011 Datasheet . Table 6: Current Sensing Resistor Selection PIN VINMIN 64W 85V Input Power Minimum Input Voltage Maximum Average Input Current I INMAX = Assume 30% Switching Frequency Ripple Peak Current with Ripple P IN 2 x ----------------V INMIN 1.06A ripple = I INMAX x 30 % i peak = I INMAX + ripple VIOVERTH1 IMARGIN 0.32A 1.38A Over Current Threshold Zone 1 (Table 5) Over Current Margin Current Sensing Resistor Calculation 0.391V 30% 0.22 V IOVERTH1 R sns = ----------------------------------------------------i peak x ( 1 + I MARGIN ) Rsns Current Sensing Resistor Selection 0.25 Table 7 shows the reference value of the current sensing resistor. In the practical design, the current sensing resistor value could be fine tuned around the value shown in the table based on the specification and the primary inductance of the Boost transformer. Table 7: Current Sensing Resistor Selection Reference 32 0.40-0.50 64 0.20-0.25 125 0.10-0.125 250 0.05-0.06 Input Power (W) Current Sensing Resistor () As the layout guideline, the current sensing signal should use Kelvin sensing connection, as shown in Figure 23. It means the SGND should layout as a separate trace from the PGND to avoid any heavy current and spike current sharing on that trace. The Vsen net should be layout as close as possible to the Rsen resistor. The same time, the Rsen resistor should be layout as close as possible to the ground as shown in Figure 23. Doc. No. MV-S104861-01 Rev. - Page 32 Document Classification: Proprietary Copyright (c) 2009 Marvell September 30, 2009, 2.00 Design and Applications Information SW Pin to MOSFET Gate 5.3.2 Over Current Limitation An adaptive current protection threshold is designed in the IC corresponding to the different input voltage in order to get the cycle by cycle current protection to avoid the transformer saturation. The four level threshold is shown in the electrical characteristic table. The universal input voltage is identified into four range from 90V to 275V. With the input voltage resistor divider ratio value as 100:1, these four ranges are 90-135V, 135-185V, 185-245V and 245V to 275V. If the resistor divider ratio value is increased from 100:1 to a higher value, these ranges will shift to the higher voltage side. On the other hand, if the resistor divider ratio value is decreased from 100:1 to a lower value, these ranges will shift to the lower voltage side. Therefore, the customer has the flexibility to adjust these ranges during the design by tuning the input voltage resistor divider ratio around the default value as 100:1. 5.4 SW Pin to MOSFET Gate The 88EM8010/88EM8011 provides a maximum 2A drive current, which is the strongest drive to date in comparison with the competition on the market. A default resistor of 10 is designed to go between the SW pin and the gate of the external MOSFET. The gate driver loop is subject to fast rise and the layout trace should be kept as short as possible in order to minimize the parasitic inductance, as shown in Figure 24. Figure 24: SW Pin Layout Guidelines Rgate Q1 Keep this trace as short as possible in layout SW VIN VDD ISNS SGND 88EM8010/ 8011 PGND FB Copyright (c) 2009 Marvell September 30, 2009, 2.00 Document Classification: Proprietary Doc. No. MV-S104861-01 Rev. - Page 33 88EM8010/88EM8011 Datasheet 5.5 VDD, Signal Ground (SGND) and Power Ground (PGND) VDD is the IC power supply pin. It has a typical value of 12V and a maximum operating voltage of 16V. A Zener circuit below 16V is recommended in order to guarantee that the voltage on VDD will not go any higher than 16V. The IC begins to function when VDD powers on at 12V. Once the IC powers on, it keeps functioning as long as the VDD is higher than VDD_UVLO, which is 7V (typical). In a practical design, an electrolytic capacitor is recommended to connect between VDD and ground in order to retain the IC functionality during startup. That capacitor will need to keep the VDD higher than 7V before the bias transformer winding takes over and provides enough energy for the power IC. A 0.01-0.1F ceramic capacitor is strongly recommended to be placed between the VDD and IC ground with the layout trace as close to the IC as possible. This capacitor is used for decoupling the noise to VDD and clamping the VDD voltage during the switching of the internal driver circuit. SGND is directly connected to the system ground by a Kelvin connection trace. The system ground is the source of the MOSFET, as shown in Figure 25. PGND connects to the system ground separately and can not share the same trace with SGND. This is due to pulse current on PGND while driving the external MOSFET on and off. This pulse current produces pulse voltage drops on the PGND trace and may cause the current sensing signal to be distorted if the SGND shares the same trace. Figure 25: VDD Decoupling Capacitor and Ground Layout Guidelines Rgate Q1 Using Kelvin sensing connection for SGND with separate trace from PGND SW VIN FB ISNS SGND PGND 88EM8010/ 8011 VDD C Keep this trace right beside IC and as short as possible Doc. No. MV-S104861-01 Rev. - Page 34 Document Classification: Proprietary Copyright (c) 2009 Marvell September 30, 2009, 2.00 5.6 Copyright (c) 2009 Marvell HVDC T2 D5 S1M +450VDC C1 0.22uF 305 VAC Q1 GATE STP8NM60 R14 10k R15 499k R9 0.2R 1W R5 600k I-SENSE R8 200R R13 499k C10 0.01uF 630VDC D6 S1M D4 STTH806DTI J2 SEC_1 SEC_2 T1 EMI FILTER + C5 47uF 250V + C4 47uF 250V C3 100uF D2 1N914 C7 4.7uF C8 4.7uF 9 + EP September 30, 2009, 2.00 J1 3A F1 AC input R4 600k D8 S1M D7 S1M C2 0.22uF 305 VAC DC output HVDC R6 600k U1 VIN VIN FB/EN C11 R7 18k 0.1nF I-SENSE 3 ISNS N/C 6 4 5 FB-EN 88EM8011 Boost PFC Schematics Figure 26: 64W/450V Front-End Boost PFC Schematic R10 487k Document Classification: Proprietary 2 SGND VDD 7 VDD12 C9 0.1uF SW 8 D1 1N91 4 SEC_1 1 PGND RGATE 10 GATE R1 100k 1/4W R11 8.66k R2 100k 1/4W VDD12 R3 10R 1/4W D3 15V 1W SEC_2 Design and Applications Information Doc. No. MV-S104861-01 Rev. - Boost PFC Schematics Page 35 POWER GROUND Figure 27: 300W/380V Front-End Boost PFC Schematic ZD1 15V SENSE GROUND SW ISNS SGND Document Classification: Proprietary R21 665k 1206 44 3 R9 200k 1206 R19 200k 1206 3 R23 200k 1206 C19 10nF R24 6.04k 2 Q2 PZT3904T1G SOT223 C5 470pF/250V R8 1.8M 1206 R7 1.8M 1206 R10 22.0k 1206 R5 1.8M 1206 Q4 1N60 SOT223 1 R4 C12 220pF/250V + C1 R11 22.0k 1206 4 PGND Page 36 D3 1N5406 C14 10uF C13 10uF 16 R22 665k 1206 1278 C10 2 1500pF/630V 1 3 R12 20K 60T 9 1 BD1 + KBU605G 1 C4 C3 470pF/250V 1uF/275V 2 3 4.5mH 4AMPS R26 0.040 2512 C7 0.33uF/630V LF1 3 2 LF2 4 1 4 Q1 IPW50R250CP R20 665k 1206 C6 1uF/275V 2 3 OPTIONAL D4 IDH08SG60C + +20VDC D2 UF4002 Doc. No. MV-S104861-01 Rev. - D1 UF4002 3T 14 L1: 250uH FA1 5A NTC1 5 C8 470pF/250V 380VDC C11 330uF/450V VDC L VAC G C9 470pF/250V 88EM8010/88EM8011 Datasheet N +20VDC +15VDC R25 200 + R13 4.99 1206 C18 OPEN R28 604k 1206 R1 ZERO 1/4W C2 330uF/25V 2 R2 1 10K R16 0 R27 604k 1206 380VDC 1 8 R18 604k 1206 +15VDC VIN VDD 7 R29 187k 88EM8011 6 N/C FB/EN 5 C16 0.1uF C17 1uF 4 R6 22.0k 1206 2 U1 C15 OPEN R14 12.7k Q3 MMBT2222A 3 3 1 2 ZD3 18V 220uF/25V OPEN ZD2 15V R3 12.0k September 30, 2009, 2.00 Copyright (c) 2009 Marvell 6.1 Mechanical Drawings September 30, 2009, 2.00 Document Classification: Proprietary Page 37 Copyright (c) 2009 Marvell Doc. No. MV-S104861-01 Rev. - 6 Figure 28: 8-Pin SOIC Mechanical Drawing Mechanical Drawings Mechanical Drawings Mechanical Drawings Notes: All dimensions in mm. See Section 7, Part Order Numbering/Package Marking, on page 39 for package marking and pin 1 location. 88EM8010/88EM8011 Datasheet THIS PAGE INTENTIONALLY LEFT BLANK Doc. No. MV-S104861-01 Rev. - Page 38 Document Classification: Proprietary Copyright (c) 2009 Marvell September 30, 2009, 2.00 Part Order Numbering/Package Marking Part Order Numbering 7 7.1 Part Order Numbering/Package Marking Part Order Numbering Figure 29 shows the part order numbering scheme. For complete ordering information, contact your Marvell FAE or sales representative. Figure 29: 88EM8010/88EM8011 Sample Ordering Part Number 88EM8011 xx-SAG2C000-xxxx Custom code (optional) Part number Custom code Custom code Temperature code C = Commercial Custom code Environmental code + = RoHS 0/6 - = RoHS 5/6 1 = RoHS 6/6 2 = Green Halogen Free Package code The standard ordering part number for the respective solution is shown in Table 8. Table 8: 88EM8010/88EM8011 Part Order Options1 Part Order Number 88EM8010xx-SAG2C000-xxxx 88EM8010xx-SAG2C000-T (Tape and Reel) 88EM8011xx-SAG2C000-xxxx 88EM8011xx-SAG2C000-T (Tape and Reel) P a c k a g e Ty p e 8-Pin SOIC 8-Pin SOIC 8-Pin SOIC 8-Pin SOIC 1. Please note that the 88EM8010 device is 60kHz and the 88EM8011 device is 120kHz. Copyright (c) 2009 Marvell September 30, 2009, 2.00 Document Classification: Proprietary Doc. No. MV-S104861-01 Rev. - Page 39 88EM8010/88EM8011 Datasheet 7.2 Package Markings Figure 30 shows a sample package marking and pin 1 location. Figure 30: Package Marking and Pin 1 Location MRVL 801X YWWG Marvell company abbreviation Abbreviated Part number XXXX = 4 character abbreviated part number Date code and lot traceability code Y = Last digit of year WW = Work Week G = lot traceability code Pin 1 location Note: The above example is not drawn to scale. Location of markings are approximate. Doc. No. MV-S104861-01 Rev. - Page 40 Document Classification: Proprietary Copyright (c) 2009 Marvell September 30, 2009, 2.00 G Table 9: Revision History Revision History D o c u m e n t R e v is i o n D o cu m e n t Ty p e 88EM8010/88EM8011 (Document = Rev. B) Break-out 8010 (60kHz) and 8011 (120kHz) Edits to Signals - Pin Descriptions EC Table edits - change in values Reworked Applications section Copyright (c) 2009 Marvell September 30, 2009, 2.00 Document Classification: Proprietary Doc. No. MV-S104861-01 Rev. - Page 41 Back Cover Marvell Semiconductor, Inc. 5488 Marvell Lane Santa Clara, CA 95054, USA Tel: 1.408.222.2500 Fax: 1.408.752.9028 www.marvell.com Marvell. Moving Forward Faster |
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